`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/12/10 13:44:03
// Design Name:
// Module Name: testALU
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module testALU(

  );

  logic [15:0] x;
  logic [15:0] y;

  logic [15:0] out;

  logic zx, nx, zy, ny, f, no;  // ALU

  logic zr, ng;

  ALU alu(x, y, zx, nx, zy, ny, f, no, out, zr, ng);
  initial
  begin
    x = 17;
    y = 5;

    {zx, nx, zy, ny, f, no} = 6'b010011;

    #10;

    assert(out == 12) else
            $error("17 - 5 failed");
    assert(zr == 0) else
            $error("17 - 5 != 0 failed");
    assert(ng == 0) else
            $error("17 - 5 > 0 failed");

  end
endmodule
